D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 33

• Manufacturer Part Number: D6417709SF167BV
• Description: IC SUPER H MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417709SF167BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figures
Figure 1.1
Figure 1.2
Figure 1.3
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3.8
Figure 3.9
Figure 3.10
Figure 3.11
Figure 3.12
Figure 3.13
Figure 3.14
Figure 4.1
Figure 4.2
Figure 4.3
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 7.1
Figure 8.1
Figure 8.2
Synonym Problem ................................................................................................ 73
Block Diagram .....................................................................................................
Pin Assignment (FP-208C, FP-208E) ..................................................................
Pin Assignment (BP-240A)..................................................................................
User Mode Register Configuration ...................................................................... 20
Privileged Mode Register Configuration.............................................................. 21
General Registers ................................................................................................. 22
System Registers .................................................................................................. 23
Register Set Overview, Control Registers ............................................................ 24
Longword ............................................................................................................. 25
Data Format in Memory ....................................................................................... 25
Processor State Transitions................................................................................... 54
MMU Functions ................................................................................................... 57
Virtual Address Space Mapping........................................................................... 59
MMU Register Contents ...................................................................................... 62
Overall Configuration of the TLB ........................................................................ 63
Virtual Address and TLB Structure...................................................................... 64
TLB Indexing (IX = 1) ......................................................................................... 65
TLB Indexing (IX = 0) ......................................................................................... 66
Objects of Address Comparison ........................................................................... 67
Operation of LDTLB Instruction.......................................................................... 71
MMU Exception Generation Flowchart ............................................................... 78
MMU Exception Signals in Instruction Fetch ...................................................... 79
MMU Exception Signals in Data Access ............................................................. 80
Specifying Address and Data for Memory-Mapped TLB Access ........................ 82
Vector Table......................................................................................................... 86
Example of Acceptance Order of General Exceptions ......................................... 89
Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers......... 92
Cache Structure .................................................................................................... 104
CCR Register Configuration ................................................................................ 106
CCR2 Register Configuration .............................................................................. 107
Cache Search Scheme (Normal Mode) ................................................................ 110
Write-Back Buffer Configuration......................................................................... 112
Specifying Address and Data for Memory-Mapped Cache Access...................... 114
Block Diagram of INTC....................................................................................... 118
Example of IRL Interrupt Connection.................................................................. 122
Interrupt Operation Flowchart .............................................................................. 144
Example of Pipeline Operations when IRL Interrupt is Accepted ....................... 148
Block Diagram of User Break Controller............................................................. 150
Canceling Standby Mode with STBCR.STBY..................................................... 189
Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output ......................... 192
Rev. 5.00, 09/03, page xxxi of xliv
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