D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 168
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Interrupts IRQ4–IRQ0 can wake the chip up from the standby state when the relevant interrupt
level is higher than the setting of I3–I0 in the SR register (but only when the RTC 32-kHz
oscillator is used).
If the IRQ edge is input immediately before the CPU enters the standby mode (during the period
between when the CPU executes a SLEEP instruction and when STATUS0 becomes high level),
the interrupt may not be detected. However, the interrupt will be accepted correctly if the IRQ
edge is re-input after the CPU has entered the standby mode (when STATUS0 is high level). In
addition, the interrupt may not be detected if the IRQ edge is input during frequency change
processing (WDT count).
6.2.3
IRL interrupts are input by level at pins IRL3–IRL0 and IRLS3–IRLS0. IRLS3–IRLS0 are
enabled when the IRQLVL bit and IRLSEN bit in interrupt control register 1 (ICR1) are both 1.
The priority level is the higher level indicated by pins IRL3–IRL0 and IRLS3–IRLS0. An IRL3–
IRL0/IRLS3–IRLS0 value of 0 (0000) indicates the highest-level interrupt request (interrupt
priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0).
Figure 6.2 shows an example of IRL interrupt connection. Table 6.3 shows IRL/IRLS pins and
interrupt levels.
Rev. 5.00, 09/03, page 122 of 760
Interrupt
request
Interrupt
request
IRL Interrupts
Figure 6.2 Example of IRL Interrupt Connection
encoder
encoder
Priority
Priority
IRLS3 to IRLS0
IRL3 to IRL0
4
4
IRLS3 to IRLS0
IRL3 to IRL0
SH7709S
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