D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 126

• Manufacturer Part Number: D6417709SF167BV
• Description: IC SUPER H MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417709SF167BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 3.13 shows the MMU exception signals in the data access mode.
3.6
To allow the management of TLB operations by software, the MOV instruction can be used, in the
privileged mode, to read and write TLB contents. The TLB is mapped to the P4 area of the virtual
address space. The TLB address array (VPN, V bit, and ASID) is mapped to H'F2000000 to
H'F2FFFFFF, and the TLB data array (PPN, PR, SZ, CD, S, and H bits) is mapped to H'F3000000
to H'F3FFFFFF. It is also possible to access the V bits in the address array from the data array.
Only longword access is possible, for both the address and data arrays.
3.6.1
The address array is mapped to H'F2000000 to H'F2FFFFFF. To access the address array, the 32-
bit address field (for read/write access) and 32-bit data field (for write access) must be specified.
The address field has the information that selects the entry to be accessed; the data field specifies
the VPN, the V bit, and the ASID to be written to the address array (figure 3.14 (1)).
Rev. 5.00, 09/03, page 80 of 760
NOP
WB
MA
EX
IF
ID
Configuration of Memory-Mapped TLB
Address Array
: Exception source stage
: Stage cancellation for instruction
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
= No operation
that has begun execution
IF
Figure 3.13 MMU Exception Signals in Data Access
ID
IF
EX
ID
IF
MMU exception handler
MA WB
EX
ID
MA WB
EX
ID
MA WB
EX
ID
MA WB
EX MA
ID
EX
WB
MA WB
IF
NOP
ID
NOP
EX
Handler transition
processing
MA WB