D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 397
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123112/d6417709sf167bv_sml.jpg)
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 397 of 809
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Figure 11.4 shows how the priority order changes when channel 0 and channel 3 transfers are
requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The
DMAC operates as follows:
1. Transfer requests are generated simultaneously for channels 0 and 3.
2. Channel 0 has a higher priority than channel 3, so the channel 0 transfer begins first (channel 3
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
4. When the channel 0 transfer ends, channel 0 becomes lowest-priority.
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
6. When the channel 1 transfer ends, channel 1 becomes lowest-priority.
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel
waits for transfer).
waiting)
(channel 3 waits for transfer).
3 becomes the lowest-priority.
Transfer request
(1) Channels 0 and 3
(3) Channel 1
Figure 11.4 Changes in Channel Priority in Round-Robin Mode
Waiting channel(s) DMAC operation
1,3
3
3
None
(2) Channel 0 transfer
(4) Channel 0 transfer
(5) Channel 1 transfer
(6) Channel 1 transfer
(7) Channel 3 transfer
(8) Channel 3 transfer
start
ends
starts
ends
starts
ends
Priority order
changes
Priority order
changes
Priority order
changes
Rev. 5.00, 09/03, page 351 of 760
Channel priority
0 > 1 > 2 > 3
1 > 2 > 3 > 0
2 > 3 > 0 > 1
0 > 1 > 2 > 3
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