D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 663
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123112/d6417709sf167bv_sml.jpg)
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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20.2
20.2.1
Upper register: H
Lower register: L
n = A to D
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte (bits 7 to 0) of the A/D data register. The lower 2 bits are stored in the lower byte (bits 7 and
6). Bits 5 to 0 of an A/D data register are reserved bits that are always read as 0. Table 20.3
indicates the pairings of analog input channels and A/D data registers.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 20.3 Analog Input Channels and A/D Data Registers
Group 0
AN0
AN1
AN2
AN3
Initial value:
Initial value:
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
R/W:
R/W:
Bit:
Bit:
Analog Input Channel
AD9
AD1
R
R
7
0
7
0
Group 1
AN4
AN5
AN6
AN7
AD8
AD0
R
R
6
0
6
0
AD7
—
R
R
5
0
5
0
AD6
—
R
R
4
0
4
0
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
AD5
—
R
R
3
0
3
0
Rev. 5.00, 09/03, page 617 of 760
AD4
—
R
R
2
0
2
0
AD3
—
R
R
1
0
1
0
AD2
—
R
R
0
0
0
0
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