D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 181
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123112/d6417709sf167bv_sml.jpg)
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 181 of 809
- Download datasheet (5Mb)
Bits 5 and 4—IRQ2 Sense Select (IRQ21S, IRQ20S): Select whether the interrupt signal to the
IRQ2 pin is detected at the rising edge, at the falling edge, or at the low level.
Bits 3 and 2—IRQ1 Sense Select (IRQ11S, IRQ10S): Select whether the interrupt signal to the
IRQ1 pin is detected at the rising edge, at the falling edge, or at the low level.
Bits 1 and 0—IRQ0 Sense Select (IRQ01S, IRQ00S): Select whether the interrupt signal to the
IRQ0 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 5: IRQ21S
0
1
Bit 3: IRQ11S
0
1
Bit 1: IRQ01S
0
1
Bit 4: IRQ20S
0
1
0
1
Bit 2: IRQ10S
0
1
0
1
Bit 0: IRQ00S
0
1
0
1
Description
An interrupt request is detected at IRQ2 input falling edge
An interrupt request is detected at IRQ2 input rising edge
An interrupt request is detected at IRQ2 input low level
Reserved
Description
An interrupt request is detected at IRQ1 input falling edge
An interrupt request is detected at IRQ1 input rising edge
An interrupt request is detected at IRQ1 input low level
Reserved
Description
An interrupt request is detected at IRQ0 input falling edge
An interrupt request is detected at IRQ0 input rising edge
An interrupt request is detected at IRQ0 input low level
Reserved
Rev. 5.00, 09/03, page 135 of 760
(Initial value)
(Initial value)
(Initial value)
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