D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 237
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123112/d6417709sf167bv_sml.jpg)
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 237 of 809
- Download datasheet (5Mb)
8.5
8.5.1
Setting the standby control register MSTP8–MSTP0 bits to 1 halts the supply of clocks to the
corresponding on-chip peripheral modules. This function can be used to reduce the power
consumption in normal mode and sleep mode. The module standby function holds the state prior
to halting the external pins of the on-chip peripheral modules. TMU external pins hold their state
prior to the halt. SCI external pins go to the reset state. With a few exceptions, all registers hold
their values.
Notes: 1. The registers initialized are the same as in standby mode (see table 8.4).
8.5.2
The module standby function can be cleared by clearing the MSTPSLP0 and MSTP8–MSTP0 bits
to 0, or by a power-on reset or manual reset.
Bit
MSTP8
MSTP7
MSTP6
MSTP5
MSTP4
MSTP3
MSTP2
MSTP1
MSTP0
2. The counter runs.
3. Before switching the RTC to module standby, access at least one among the registers
Module Standby Function
Transition to Module Standby Function
Clearing Module Standby Function
RTC, SCI, and TMU.
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
UBC runs
Supply of clock to UBC halted
DMAC runs
Supply of clock to DMAC halted
DAC runs
Supply of clock to DAC halted
ADC runs
Supply of clock to ADC halted, and all registers initialized
SCIF runs
Supply of clock to SCIF halted
IrDA runs
Supply of clock to IrDA halted
TMU runs
Supply of clock to TMU halted. Registers initialized *
RTC runs
Supply of clock to RTC halted. Register access prohibited *
SCI runs
Supply of clock to SCI halted
Rev. 5.00, 09/03, page 191 of 760
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