D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 650
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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19.10.2 Port J Data Register (PJDR)
The port J data register (PJDR) is an 8-bit readable/writable register that stores data for pins PTJ7
to PTJ0. Bits PJ7DT to PJ0DT correspond to pins PTJ7 to PTJ0. When the pin function is general
output port, if the port is read the value of the corresponding PJDR bit is returned directly. When
the function is general input port, if the port is read, the corresponding pin level is read. Table
19.18 shows the function of PJDR.
PJDR is initialized to H'00 by a power-on reset. It retains its previous value in software standby
mode and sleep mode, and in a manual reset.
Table 19.18 Port J Data Register (PJDR) Read/Write Operations
PJnMD1
0
1
Rev. 5.00, 09/03, page 604 of 760
Initial value:
PJnMD0
0
1
0
1
R/W:
Bit:
PJ7DT
R/W
7
0
Pin State
Other function
(see table 18.1)
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
PJ6DT
R/W
6
0
PJ5DT
R/W
Read
PJDR value
PJDR value
Pin state
Pin state
5
0
PJ4DT
R/W
4
0
Write
Value is written to PJDR, but does not
affect pin state
Write value is output from pin
Value is written to PJDR, but does not
affect pin state
Value is written to PJDR, but does not
affect pin state
PJ3DT
R/W
3
0
PJ2DT
R/W
2
0
PJ1DT
R/W
1
0
(n = 0 to 7)
PJ0DT
R/W
0
0
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