D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 84
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 2.5 lists the SH7709S instruction code formats.
Table 2.5
Item
Instruction
mnemonic
Instruction
code
Operation
summary
Privileged
mode
Execution
cycles
T bit
Note: * Scaling ( 1, 2, 4) is performed according to the instruction operand size.
Rev. 5.00, 09/03, page 38 of 760
Instruction Code Format
Format
OP.Sz SRC,DEST
MSB
(xx)
M/Q/T
&
|
^
~
<<n, >>n
,
LSB
Explanation
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement *
Direction of transfer
Memory operand
Flag bits in SR
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit shift
Indicates whether privileged mode applies
Value when no wait states are inserted
The execution cycles listed in the table are minimums. The
actual number of cycles may be increased in cases such as
the followsing:
1. When contention occurs between instruction fetches and
2. When the destination register of the load instruction
Value of T bit after instruction is executed
—: No change
data access
(memory
instruction are the same
0000: R0
0001: R1
1111: R15
...........
register) and the register used by the next
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