ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 117

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20. Voltage ADC – 7-channel General Purpose 12-bit Sigma-Delta ADC
20.1
20.2
20.3
8042B–AVR–06/10
Features
Overview
Operation
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The ATmega16HVB/32HVB features a 12-bit Sigma-Delta ADC.
The Voltage ADC (V-ADC) is connected to seven different sources through the Input Multi-
plexer. There are four differential channels for Cell Voltage measurements. These channels are
scaled 0.2x to comply with the Full Scale range of the V-ADC. In addition there are three single
ended channels referenced to SGND. One channel is for measuring the internal temperature
sensor VPTAT and two channels for measuring the voltage at ADC0 and ADC1.
When the V-ADC is not used, power consumption can be minimized by writing the PRVADC bit
in PRR0 to one. See
the PRVADC bit.
Figure 20-1. Voltage ADC Block Schematic
To enable V-ADC conversions, the V-ADC Enable bit, VADEN, in V-ADC Control and Status
Register – VADCSR must be set. If this bit is cleared, the V-ADC will be switched off, and any
ongoing conversions will be terminated. The V-ADC is automatically disabled in Power-save and
12-bit Resolution
519µs Conversion Time @ 1 MHz clk
Four Differential Input Channels for Cell Voltage Measurements
Three Single Ended Input Channels
0.2x Pre-scaling of Cell Voltages
Interrupt on V-ADC Conversion Complete
ADC1/SGND
ADC0/SGND
VTEMP
PV4
PV3
PV2
PV1
NV
Note:
The shaded signals are scaled by 0.2,
other signals are scaled by 1.0
”PRR0 – Power Reduction Register 0” on page 40
INPUT
MUX
VADC
SIGMA-DELTA ADC
VREF
V-ADC MULTIPLEXER
8-BIT DATA BUS
V-ADC CONTROL
SEL. REG (VADMUX)
12-BIT
SGND
ATmega16HVB/32HVB
V-ADC CONVERSION COMPLETE IRQ
STATUS REG (VADCSR)
V-ADC DATA REGISTER
V-ADC CONTROL AND
(VADCL/ADCH)
for details on how to use
117