ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 121

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4.3
8042B–AVR–06/10
VADCL and VADCH – V-ADC Data Register
VADSC will read as one as long as the conversion is not finished. When the conversion is com-
plete, it returns to zero. Writing zero to this bit has no effect. VADSC will automatically be
cleared when the VADEN bit is written to zero.
• Bit 1 – VADCCIF: V-ADC Conversion Complete Interrupt Flag
This bit is set when a V-ADC conversion completes and the data registers are updated. The V-
ADC Conversion Complete Interrupt is executed if the VADCCIE bit and the I-bit in SREG are
set. VADCCIF is cleared by hardware when executing the corresponding interrupt handling vec-
tor. Alternatively, VADCCIF is cleared by writing a logical one to the flag. Beware that if doing a
Read-Modify-Write on VADCSR, a pending interrupt can be lost.
• Bit 0 – VADCCIE: V-ADC Conversion Complete Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the V-ADC Conversion Complete
Interrupt is activated.
When a V-ADC conversion is complete, the result is found in these two registers. To ensure that
correct data is read, both high and low byte data registers should be read before starting a new
conversion.
• VADC11:0: V-ADC Conversion Result
These bits represent the result from the conversion.
To obtain the best absolute accuracy for the cell voltage measurements, gain and offset com-
pensation is required. Factory calibration values are stored in the device signature row, refer to
section
mV is given by:
The voltage on the ADCn is given by:
When performing a Vtemp conversion, the result must be adjusted by the factory calibration
value stored in the signature row, refer to section
page 199
Bit
(0x79)
(0x78)
Read/Write
Initial Value
ADCn[mV]
”Reading the Signature Row from Software” on page 199
for details. The absolute temperature in Kelvin is given by:
Cell
n
[mV]
15
R
R
–
7
0
0
=
----- - (VADCH/L VADC ADCn Offset)
10
1
=
⋅
(VADCH/L VADC Cell
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
14
R
R
–
6
0
0
–
–
13
R
R
–
5
0
0
12
n
R
R
–
4
0
0
Offset)
VADC[7:0]
”Reading the Signature Row from Software” on
16384
⋅
ATmega16HVB/32HVB
11
16384
VADC Cell
3
R
R
0
0
⋅
VADC ADCn Gain Calibration Word
10
R
R
0
2
0
n
VADC[11:8]
Gain Calibration Word
for details. The cell voltage in
R
R
9
1
0
0
R
R
8
0
0
0
VADCH
VADCL
121