ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 127

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.6.3
8042B–AVR–06/10
BGCSR – Bandgap control and Status Register
Figure 21-2.
•
These bits are reserved and will always read as zero.
•
Setting this bit to one will disable the bandgap voltage reference. This bit must be cleared (zero)
before enabling Cell Balancing, CC-ADC, V-ADC or Battery Protection, and must remain unset
(zero) while either of these modules are enabled. Note that after clearing this bit, a settling time
is required before the voltage is stable, see
•
Setting this bit to one will enable the bandgap Short Circuit Detector. This bit should be cleared if
the BGD bit in the BGCSR is set to one to avoid false setting of the BGSCDIF bit.
•
These bits are reserved and will always read as zero.
•
The bit is set when the Bandgap Short Circuit Detector is enabled and buffered bandgap refer-
ence is different from the unbuffered Bandgap reference. The BGSCDIF is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, BGSCDIF is cleared
by writing a logic one to its bit position.
Bit
(0xD2)
Read/Write
Initial Value
Bits 7:6 – Reserved
Bit 5 – BGD: Bandgap Disable
Bit 4 – BGSCDE: Bandgap Short Circuit Detection Enabled
Bits 3:2 – Reserved
Bit 1 – BGSCDIF: Bandgap Short Circuit Detection Interrupt Flag
R
7
–
0
R
6
–
0
BGD
R/W
5
0
BGSCDE
R/W
4
0
”Bandgap Buffer Settling Time” on page
ATmega16HVB/32HVB
R
3
–
0
R
2
–
0
BGSCDIF
R/W
1
0
BGSCDIE
R/W
0
0
124.
BGCSR
127