ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 131

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.4
22.4.1
8042B–AVR–06/10
Register Description
CHGDCSR – Charger Detect Control and Status Register
•
• Bit 7:5 – Reserved
These bits are reserved and will always read as zero.
• Bit 4 – BATTPVL: BATT pin Voltage Level
BATTPVL will read one as long when the Charger Detect module is enabled and the BATT pin
voltage is above the VPOT level. Otherwise the BATTPVL will read zero.
• Bit 3:2 – CHGDISC[1:0]: Charger Detect Interrupt Sense Control
Edges in the CHARGER_PRESENT signal shown in
vate a Charger Detect Interrupt if the SREG I-flag and the interrupt enable bit in CHGDCSR are
set. By writing the CHGDISC bits to the values shown in
generating interrupt is configured. When changing the CHGDISC bits, an interrupt can occur.
Therefore, it is recommended to first disable the Interrupt by clearing its CHGDIE bit in the
CHGDICSR Register. Finally, the Charger Detect interrupt flag should be cleared by writing a
logical one to CHGDIF bit before the interrupt is re-enabled.
Table 22-1.
• Bit 1 – CHGDIF: Charger Detect Interrupt Flag
Depending on the configuration of the CHGDISC bits in the CHGDCSR, this bit is set when a
charger is either connected or disconnected. The Charger Detect Interrupt is executed if the
CHGDIE bit and the I-bit in SREG are set. This bit is cleared by hardware when executing the
corresponding interrupt handling vector or alternatively by writing a logical one to the CHGDIF. It
is recommended to write this bit to one when setting CHGDIE.
• Bit 0 – CHGDIE: Charger Detect Interrupt Enable
When the CHGDIE bit is set (one), and the I-bit in the Status Register is set (one), the Charger
Detect Interrupt is enabled.
Bit
(0xD4)
Read/Write
Initial Value
When disabling the Charge-FET the Charger Detect module is automatically enabled and a
charger appear to be connected.
CHGISC[1:0]
R
7
–
0
00
01
10
11
Charger Detect Interrupt Sense Control.
R
6
–
0
R
5
–
0
BATTPVL
Detection
Charger Connect
Charger Disconnect
Charger Connect/Disconnect
None
R
4
0
CHGDISC1
R/W
3
0
ATmega16HVB/32HVB
CHGDISC0
Figure 22-1 on page 129
R/W
2
0
Table 22-1 on page 131
CHGDIF
R/W
1
0
CHGDIE
R/W
are used to acti-
0
0
the condition
CHGDCSR
131