ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 118

• Manufacturer Part Number: ATMEGA32HVB-8X3
• Description: MCU AVR 32KB FLASH 8MHZ 44TSSOP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32HVB-8X3

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: POR, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 7x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSSOP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 7 Channel
• Package: 44TSSOP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5|9|12|15|18|24 V
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.1
8042B–AVR–06/10
Configuring PA1 and PA0 for V-ADC operation
Power-off mode. Note that the bandgap voltage reference must be enabled and disabled sepa-
rately, see
Figure 20-2. Voltage ADC Conversion Diagram
To perform a V-ADC conversion, the analog input channel must first be selected by writing to the
VADMUX register. When a logical one is written to the V-ADC Start Conversion bit VADSC, a
conversion of the selected channel will start. The VADSC bit stays high as long as the conver-
sion is in progress and will be cleared by hardware when the conversion is completed. When a
conversion is in progress, the V-ADC Data Register - VADCL and VADCH will be invalid. If the
System Clock Prescaler setting is changed during a V-ADC conversion, the conversion will be
aborted. If a different data channel is selected while a conversion is in progress, the ADC will fin-
ish the current conversion before performing the channel change. When a conversion is finished
the V-ADC Conversion Complete Interrupt Flag – VADCCIF is set. One 12-bit conversion takes
519 µs to complete from the start bit is set to the interrupt flag is set. The V-ADC Data Register -
VADCL and VADCH will be valid until a new conversion is started. To ensure that correct data is
read, both high and low byte data registers should be read before starting a new conversion.
When one of the single ended channels ADC0 or ADC1 is used as analog input to the VADC,
either PA0 or PA1 are used as signal ground (SGND). When ADC0/1 is selected as input chan-
nel, PA1/0 is automatically switched to SGND.
The use of PA1 and PA0 as SGND is efficient for the thermistor configuration shown in
ing Circuit” on page
divider resistor, R31, to PA0 and PA1 respectively.
Both PA0 and PA1 have very high input impedance when used as ADC inputs, which makes it
possible to connect two thermistors in the configuration, shown in
225. However, input impedance is limited and if high accuracy is required, only one thermistor
should be connected between PA0 and PA1. If two thermistors are connected, the configuration
is as follows:
• When measuring RT33, PA1 should be used as input channel and PA0 is automatically
• When measuring RT32, PA0 should be used as input channel and PA1 is automatically
Conversion Result
switched to SGND.
switched to SGND.
Start Conversion
Interrupt
”Bandgap Calibration” on page
OLD DATA
225. Both thermistors, RT32 and RT33 are connected through a common
INVALID DATA
124.
V A L I D
ATmega16HVB/32HVB
D ATA
”Operating Circuit” on page
INVALID DATA
”Operat-
118