ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 12

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
Table 1 : Ball Description (continued)
12/186
RD
WR/WRL
READY/
READY
ALE
EA
PORT0:
P0L.0 - P0L.7,
P0H.0 - P0H.7
Symbol
Number
G16
G15
G14
Ball
H17
H16
H15
H14
E17
E16
D17
E15
D16
C17
E14
F16
F15
F14
J14
J15
J16
J17
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
External Memory Read Strobe. RD is activated for every external instruction or
data read access.
External Memory Write Strobe. In WR-mode this pin is activated for every
external data write access. In WRL-mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
Ready Input. The active level is programmable. When the Ready function is
enabled, the selected inactive level at this pin during an external memory access
will force the insertion of memory cycle time waitstates until the pin returns to the
selected active level.
Address Latch Enable Output. Can be used for latching the address into external
memory or an address latch in the multiplexed bus modes.
External Access Enable pin. A low level at this pin during and after Reset forces
the ST10F280 to begin instruction execution out of external memory. A high level
forces execution out of the internal Flash Memory.
PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise
programmable for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as the address (A) and
address/data (AD) bus in multiplexed bus modes and as the data (D) bus in
demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width:
P0L.0 – P0L.7:
P0H.0 – P0H.7:
Multiplexed bus modes:
Data Path Width:
P0L.0 – P0L.7:
P0H.0 – P0H.7:
P0L.0
P0L.1
P0L.2
P0L.3
P0L.4
P0L.5
P0L.6
P0L.7
P0H.0
P0H.1
P0H.2
P0H.3
P0H.4
P0H.5
P0H.6
P0H.7
8-bit
D0 - D7
I/O
8-bit
AD0 - AD7
A8 - A15
Function
16-bit
D0 - D7
D8 - D15
16-bit
AD0 - AD7
AD8 - AD15