ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 96

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
P7 (FFD0h / E8h)
DP7 (FFD2h / E9h)
ODP7 (F1D2h / E9h)
12.9.1 - Alternate Functions of Port 7
The upper 4 lines of Port 7 (P7.7...P7.4) serve as
capture
(CC31IO...CC28IO) for the CAPCOM2 unit.
The usage of the port lines by the CAPCOM unit,
its accessibility via software and the precautions
are the same as described for the Port 2 lines.
As all other capture inputs, the capture input func-
tion of pins P7.7...P7.4 can also be used as exter-
nal interrupt inputs (200 ns sample rate at 40MHz
CPU clock).
Table 19 : Port 7 Alternate Functions
96/186
P7.y
DP7.y
ODP7.y
15
15
15
Port 7 Pin
-
-
-
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
14
-
14
14
-
-
inputs
13
-
POUT0
POUT1
POUT2
POUT3
CC28IO
CC29IO
CC30IO
CC31IO
13
13
-
-
12
Port data register P7 bit y
Port direction register DP7 bit y
DP7.y = 0: Port line P7.y is an input (high impedance)
DP7.y = 1: Port line P7.y is an output
Port 7 Open Drain control register bit y
ODP7.y = 0: Port line P7.y output driver in push-pull mode
ODP7.y = 1: Port line P7.y output driver in open drain mode
-
12
12
-
-
or
11
-
PWM mode channel 0 output
PWM mode channel 1 output
PWM mode channel 2 output
PWM mode channel 3 output
Capture input / compare output channel 28
Capture input / compare output channel 29
Capture input / compare output channel 30
Capture input / compare output channel 31
10
11
11
-
-
-
compare
9
-
10
10
-
-
8
-
9
9
-
-
outputs
ODP7.7 ODP7.6 ODP7.5 ODP7.4 ODP7.3 ODP7.2 ODP7.1 ODP7.0
RW
7
8
8
-
-
ESFR
SFR
SFR
Alternate Function
RW
DP7.7 DP7.6 DP7.5 DP7.4 DP7.3 DP7.2 DP7.1 DP7.0
P7.7
6
RW
RW
The lower 4 lines of Port 7 (P7.3...P7.0) serve as
outputs
(POUT3...POUT0). At these pins the value of the
respective port output latch is XORed with the
value of the PWM output rather than ANDed, as
the other pins do. This allows to use the alternate
output value either as it is (port latch holds a ‘0’) or
invert its level at the pin (port latch holds a ‘1’).
Note that the PWM outputs must be enabled via
the respective PENx bits in PWMCON1.
The table below summarizes the alternate func-
tions of Port 7.
7
7
P7.6
RW
RW
RW
5
6
6
P7.5
RW
RW
from
RW
5
5
4
P7.4
RW
RW
4
4
RW
3
the
P7.3
RW
RW
3
3
RW
Reset Value: - - 00h
Reset Value: - - 00h
Reset Value: - - 00h
2
PWM
P7.2
RW
RW
2
2
RW
1
P7.1
RW
RW
1
1
module
RW
P7.0
RW
RW
0
0
0