ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 135

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18 - POWER REDUCTION MODES
Two different power reduction modes with differ-
ent levels of power reduction have been imple-
mented in the ST10F280, which may be entered
under software control.
In Idle mode the CPU is stopped, while the
peripherals continue their operation. Idle mode
can be terminated by any reset or interrupt
request.
In Power Down mode both the CPU and the
peripherals are stopped. Power Down mode can
now be configured by software in order to be ter-
minated only by a hardware reset or by a transi-
tion on enabled fast external interrupt pins.
Note: All external bus actions are completed
18.1 - Idle Mode
Idle mode is entered by running IDLE protected
instruction. The CPU operation is stopped and the
peripherals still run.
Idle mode is terminate by any interrupt request.
Whatever the interrupt is serviced or not, the
instruction following the IDLE instruction will be
SYSCON (FF12h / 89h)
Note: Register SYSCON cannot be changed after execution of the EINIT instruction.
PWDCFG
15
STKSZ
Bit
RW
14
before Idle or Power Down mode is
entered. However, Idle or Power Down
mode is not entered if READY is enabled,
but has not been activated (driven low for
negative polarity, or driven high for positive
polarity) during the last bus access.
13
0
1
ROM
RW
S1
12
Power Down Mode Configuration Control
Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, oth-
erwise the instruction has no effect. To exit Power Down Mode, an external reset must occurs by
asserting the RSTIN pin.
Power Down Mode can only be entered during PWRDN instruction execution if all enabled Fas-
tExternal Interrupt (EXxIN) pins are in their inactive level. Exiting this mode can be done by
asserting one enabled EXxIN pin.
SGT
DIS
RW
11
ROM
RW
EN
10
BYT
DIS
RW
9
CLK
RW
EN
8
SFR
CFG
RW
WR
7
Function
executed after return from interrupt (RETI)
instruction, then the CPU resumes the normal
program.
Note that a PEC transfer keep the CPU in Idle
mode. If the PEC transfer does not succeed, the
Idle mode is terminated. Watchdog timer must be
properly programmed to avoid any disturbance
during Idle mode.
18.2 - Power Down Mode
Power Down mode starts by running PWRDN
protected instruction. Internal clock is stopped, all
MCU parts are on hold including the watchdog
timer.
There are two different operating Power Down
modes : protected mode and interruptible mode.
The internal RAM contents can be preserved
through the voltage supplied via the V
verify RAM integrity, some dedicated patterns
may be written before entering the Power Down
mode and have to be checked after Power Down
is resumed.
It is mandatory to keep V
power-down mode, because
voltage regulator is turned in power saving
mode and it delivers 2.5V to the core logic, but
it must be supplied at nominal V
CFG
RW
CS
6
PWD-
CFG
RW
5
OWD-
DIS
RW
4
STEN
BDR
RW
3
DD
XPEN
= +5V ±10% during
RW
Reset Value: 0xx0h
2
DD
the
VISI
BLE
RW
1
ST10F280
= +5V.
DD
on-chip
pins. To
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