ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 52

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
Hardware traps are exceptions or error conditions
that arise during run-time. They cause immediate
non-maskable system reaction similar to a
standard
dedicated vector table location).
The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag
register (TFR). Except when another higher
prioritized trap service is in progress, a hardware
trap will interrupt any other program execution.
Hardware trap services cannot not be interrupted
by standard interrupt or by PEC interrupts.
8.3 - Interrupt Control Registers
All interrupt control registers are identically
organized. The lower 8 bit of an interrupt control
register contain the complete interrupt status
xxIC (yyyyh / zzh)
52/186
15
-
GLVL
ILVL
xxIR
xxIE
Bit
14
-
interrupt service
13
-
Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
12
-
11
-
(branching to
10
-
9
-
SFR Area
8
-
a
xxIR
RW
information of the associated source, which is
required during one round of prioritization, the
upper 8 bit of the respective register are reserved.
All interrupt control registers are bit-addressable
and all bit can be read or written via software.
This
programmed or modified with just one instruction.
When
through instructions which operate on Word data
types, their upper 8 bit (15...8) will return zeros,
when read, and will discard written data.
The layout of the Interrupt Control registers shown
below applies to each xxIC register, where xx
stands for the mnemonic for the respective
source.
7
Function
xxIE
RW
allows
6
accessing
5
each
4
interrupt
ILVL
RW
interrupt
3
Reset Value: - - 00h
control
2
source
1
GLVL
registers
RW
to
0
be