ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 165

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.4.10 - Multiplexed Bus
V
ALE cycle time = 6 TCL + 2t
Table 41 : Multiplexed Bus Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
22
23
25
27
38
39
40
DD
Symbol
= 5V
CC
CC
CC
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
CC
SR
CC
10%, V
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD, WR
(with RW-delay)
ALE falling edge to RD, WR (no
RW-delay)
Address float after RD, WR
(with RW-delay)
Address float after RD, WR
(no RW-delay)
RD, WR low time
(with RW-delay)
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
Address/Unlatched CS to valid
data in
Data hold after RD
rising edge
Data float after RD
Data valid to WR
Data hold after WR
ALE rising edge after RD, WR
Address/Unlatched CS hold
after RD, WR
ALE falling edge to Latched CS
Latched CS low to Valid Data In
Latched CS hold after RD, WR
(no RW-delay)
(with RW-delay)
(no RW-delay)
SS
Parameter
= 0V, T
A
A
+ t
= -40 to +125°C, C
C
+ t
F
(75ns at 40MHz CPU clock without wait states).
1
1
1
1
15.5 + t
-8.5 + t
28 + t
10 + t
15 + t
10 + t
27 + t
4 + t
2 + t
4 + t
4 + t
-4 - t
4 + t
min.
Max. CPU Clock
–
–
–
–
–
–
0
–
–
A
A
A
A
F
A
C
C
F
F
F
= 40MHz
A
C
L
= 50pF,
18.5 + t
22 + 2t
18.5 + t
+ t
16.5 + t
10 - t
6 + t
max.
18.5
18.5
A
2t
t
–
–
–
–
–
6
–
–
–
–
–
–
–
–
C
+ t
A
C
A
A
C
C
C
F
+
+
3 TCL - 10.5 + t
2 TCL - 8.5 + t
TCL - 10.5 + t
2 TCL -9.5 + t
3 TCL -9.5 + t
2 TCL -15 + t
2 TCL -10 + t
2 TCL -15 + t
TCL - 8.5 + t
TCL - 8.5 + t
TCL - 8.5 + t
-8.5 + t
-4 - t
min.
1/2 TCL = 1 to 40MHz
Variable CPU Clock
–
–
–
–
–
–
0
–
–
A
A
A
A
A
C
F
F
A
C
C
F
F
2 TCL - 8.5 + t
2 TCL - 19 + t
3 TCL - 19 + t
3 TCL - 19
4 TCL - 28
3 TCL - 19
+ 2t
+ t
+ t
TCL + 6
10 - t
max.
C
A
A
–
–
–
–
–
6
–
–
–
–
–
–
–
–
+ 2t
+ t
+ t
A
ST10F280
C
C
A
C
C
F
165/186
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns