ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 70

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
12 - PARALLEL PORTS
In order to accept or generate single external con-
trol signals or parallel data, the ST10F280 pro-
vides up to 143 parallel I/O lines, organized into
two 16-bit I/O port (Port 2, XPort9), eight 8-bit I/O
ports (PORT0 made of P0H and P0L, PORT1
made of P1H and P1L, Port 4, Port 6, Port 7,
Port 8) , one 15-bit I/O port (Port 3) and two 16-bit
input port (Port 5, XPort10).
These port lines may be used for general purpose
Input/Output, controlled via software, or may be
used implicitly by ST10F280’s integrated periph-
erals or the External Bus Controller.
All port lines are bit addressable, and all input/out-
put lines are individually (bit-wise) programmable
as inputs or outputs via direction registers (except
Port 5, XPort10). The I/O ports are true bidirec-
tional ports which are switched to high impedance
state when configured as inputs. The output driv-
ers of seven I/O ports (2, 3, 4, 6, 7, 8, 9) can be
configured (pin by pin) for push/pull operation or
open-drain operation via ODPx control registers.
The output driver of the pads are programmable to
adapt the edge characteristics to the application
requirement and to improve the EMI behaviour.
This is possible using the POCONx registers for
Ports P0L, P0H, P1L, P1H, P2, P3, P4, P6, P7,
P8. The output driver capabilities of ALE, RD and
WR control lines are programmable with the dedi-
cated bits of POCON20 control register.
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The input threshold levels are programmable
(TTL/CMOS) for five ports (2, 3, 4, 7, 8) with the
PICON register control bits. The logic level of a pin
is clocked into the input latch once per state time,
regardless whether the port is configured for input
or output.
A write operation to a port pin configured as an
input causes the value to be written into the port
output latch, while a read operation returns the
latched state of the pin itself. A read-modify-write
operation reads the value of the pin, modifies it,
and writes it back to the output latch.
Writing to a pin configured as an output
(DPx.y=‘1’) causes the output latch and the pin to
have the written value, since the output buffer is
enabled. Reading this pin returns the value of the
output latch. A read-modify-write operation reads
the value of the output latch, modifies it, and
writes it back to the output latch, thus also modify-
ing the level at the pin.
Note: The new I/O ports (XPort9, XPort10) are
not mapped on the SFR space but on the
internal XBUS interface . The XPort9 and
XPort10 are enabled by setting XPEN bit 2
of the SYSCON register and bit 3 of the
new XPERCON register. On the XBUS
interface, the registers are not bit-address-
able.