ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 94

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
ODP6 (F1CEh / E7h)
12.8.1 - Alternate Functions of Port 6
A programmable number of chip select signals (CS4...CS0) derived from the bus control registers
(BUSCON4...BUSCON0) can be output on the 5 pins of Port 6. The number of chip select signals is
selected via PORT0 during reset. The selected value can be read from bitfield CSSEL in register RP0H
(read only) e.g. in order to check the configuration during run time. The table below summarizes the alter-
nate functions of Port 6 depending on the number of selected chip select lines (coded via bitfield CSSEL).
Table 18 : Port 6 Alternate Functions
Figure 44 : Port 6 I/O and Alternate Functions
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DP6.y
ODP6.y
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
15
Port 6 Pin
-
Bit
Bit
14
-
13
-
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
HOLD External hold request input
HLDA Hold acknowledge output
BREQ Bus request output
Altern. Function
Port direction register DP6 bit y
DP6.y = 0: Port line P6.y is an input (high-impedance)
DP6.y = 1: Port line P6.y is an output
Port 6 Open Drain control register bit y
ODP6.y = 0: Port line P6.y output driver in push/pull mode
ODP6.y = 1: Port line P6.y output driver in open drain mode
12
CSSEL = 10
-
General Purpose Input/Output
Port 6
Alternate Function
11
-
10
-
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
Chip select CS0
Chip select CS1
Gen. purpose I/O
Gen. purpose I/O
Gen. purpose I/O
9
-
Altern. Function
CSSEL = 01
8
-
ODP6.7ODP6.6ODP6.5 ODP6.4 ODP6.3 ODP6.2 ODP6.1 ODP6.0
RW
ESFR
7
RW
Function
Function
6
Chip select CS0
Chip select CS1
Chip select CS2
Gen. purpose I/O
Gen. purpose I/O
Altern. Function
RW
5
CSSEL = 00
a)
RW
4
BREQ
HLDA
HOLD
CS4
CS3
CS2
CS1
CS0
RW
3
Chip select CS0
Chip select CS1
Chip select CS2
Chip select CS3
Chip select CS4
Reset Value: - - 00h
RW
Altern. Function
2
CSSEL = 11
RW
1
RW
0