ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 127

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16 - WATCHDOG TIMER
The Watchdog Timer is a fail-safe mechanism
which prevents the microcontroller from malfunc-
tioning for long periods of time.
The Watchdog Timer is always enabled after a
reset of the chip and can only be disabled in the
time interval until the EINIT (end of initialization)
instruction has been executed.
Therefore, the chip start-up procedure is always
monitored. The software must be designed to ser-
vice the watchdog timer before it overflows. If, due
WDTCON (FFAEh / D7h)
Notes: 1. More than one reset indication flag may be set. After EINIT, all flags are cleared.
WDTIN
WDTR
SWR
SHWR
LHWR
PONR
15
2. Power-on is detected when a rising edge from Vcc = 0 V to Vcc > 2.0 V is recognized.
1
14
1- 2
1
1
1
13
Watchdog Timer Input Frequency Selection
‘0’: Input Frequency is f
‘1’: Input Frequency is f
Watchdog Timer Reset Indication Flag
Set by the watchdog timer on an overflow.
Cleared by a hardware reset or by the SRVWDT instruction.
Software Reset Indication Flag
Set by the SRST execution.
Cleared by the EINIT instruction.
Short Hardware Reset Indication Flag
Set by the input RSTIN.
Cleared by the EINIT instruction.
Long Hardware Reset Indication Flag
Set by the input RSTIN.
Cleared by the EINIT instruction.
Power-On (Asynchronous) Reset Indication Flag
Set by the input RSTIN if a power-on condition has been detected.
Cleared by the EINIT instruction.
WDTREL
12
RW
11
10
9
8
CPU
CPU
/2.
/128.
7
-
SFR
6
-
to hardware or software related failures, the soft-
ware fails to do so, the watchdog timer overflows
and generates an internal hardware reset. It pulls
the RSTOUT pin low in order to allow external
hardware components to be reset.
Each of the different reset sources is indicated in
the WDTCON register.
The indicated bit are cleared with the EINIT
instruction. The origine of the reset can be identi-
fied during the initialization phase.
PONR LHWR SHWR
R
5
R
4
R
3
SWR
R
Reset Value: 00xxh
2
WDTR WDTIN
R
1
ST10F280
127/186
RW
0