ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 142

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ST10F280

Manufacturer Part Number
ST10F280
Description
MCU 16BIT 512K FLASH MAC 208-PBG
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F280

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, SSC
Peripherals
POR, PWM, WDT
Number Of I /o
143
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
18K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 32x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
208-PBGA
Processor Series
ST10F28x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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ST10F280
Table 35 : Special Function Registers Listed by Name (continued)
142/186
DPP0
DPP1
DPP2
DPP3
EXICON
EXISEL
IDCHIP
IDMANUF
IDMEM
IDPROG
IDX0
IDX1
MAH
MAL
MCW
MDC
MDH
MDL
MRW
MSW
ODP2
ODP3
ODP4
ODP6
ODP7
ODP8
ONES
P0L
P0H
P1L
P1H
P2
P3
P4
P5
P6
Name
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
FE00h
FE02h
FE04h
FE06h
F1C0h
F1DAh
F07Ch
F07Eh
F07Ah
F078h
FF08h
FF0Ah
FE5Eh
FE5Ch
FFDCh
FF0Eh
FE0Ch
FE0Eh
FFDAh
FFDEh
F1C2h
F1C6h
F1CAh
F1CEh
F1D2h
F1D6h
FF1Eh
FF00h
FF02h
FF04h
FF06h
FFC0h
FFC4h
FFC8h
FFA2h
FFCCh
Physical
address
E
E
E
E
E
E
E
E
E
E
E
E
address
8-bit
EDh
EDh
E0h
3Eh
3Dh
3Ch
2Eh
EEh
EFh
E1h
E3h
E5h
E7h
E9h
EBh
E0h
E2h
E4h
D1h
E6h
00h
01h
02h
03h
3Fh
84h
85h
2Fh
87h
06h
07h
8Fh
80h
81h
82h
83h
CPU Data Page Pointer 0 Register (10-bit)
CPU Data Page Pointer 1 Register (10-bit)
CPU Data Page Pointer 2 Register (10-bit)
CPU Data Page Pointer 3 Register (10-bit)
External Interrupt Control Register
External Interrupt Source Selection Register
Device Identifier Register (n is the device revision)
Manufacturer Identifier Register
On-chip Memory Identifier Register
Programming Voltage Identifier Register
MAC Unit Address Pointer 0
MAC Unit Address Pointer 1
MAC Unit Accumulator - High Word
MAC Unit Accumulator - Low Word
MAC Unit Control Word
CPU Multiply Divide Control Register
CPU Multiply Divide Register – High Word
CPU Multiply Divide Register – Low Word
MAC Unit Repeat Word
MAC Unit Status Word
Port 2 Open Drain Control Register
Port 3 Open Drain Control Register
Port 4 Open Drain Control Register
Port 6 Open Drain Control Register
Port 7 Open Drain Control Register
Port 8 Open Drain Control Register
Constant Value 1’s Register (read only)
PORT0 Low Register (Lower half of PORT0)
PORT0 High Register (Upper half of PORT0)
PORT1 Low Register (Lower half of PORT1)
PORT1 High Register (Upper half of PORT1)
Port 2 Register
Port 3 Register
Port 4 Register (8-bit)
Port 5 Register (read only)
Port 6 Register (8-bit)
Description
XXXXh
FFFFh
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
- - 00h
Reset
0000h
0001h
0002h
0003h
0000h
0000h
118nh
0401h
3080h
0040h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0200h
0000h
0000h
0000h
0000h
value

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