ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 47

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 11 : Chip Select Delay
7.2 - READY Programmable Polarity
The active level of the READY pin can be selected by software via the RDYPOL bit in the BUSCONx reg-
isters. When the READY function is enabled for a specific address window, each bus cycle within this win-
dow must be terminated with the active level defined by this RDYPOL bit in the associted BUSCON
register.
BUSCON0 (FF0Ch / 86h)
BUSCON1 (FF14h / 8Ah)
BUSCON2 (FF16h / 8Bh)
CSW
CSW
CSW
EN0
EN1
EN2
RW
RW
RW
15
15
15
CSRE
CSR
CSR
EN1
EN2
RW
RW
RW
N0
14
14
14
Unlatched CSx
Segment (P4)
Address (P1)
POL0
POL1
POL2
RDY
RDY
RDY
Normal CSx
RW
RW
RW
13
13
13
BUS (P0)
BUS (P0)
ALE
WR
RDY
EN0
RDY
EN1
RDY
EN2
RD
RW
RW
RW
12
12
12
11
11
11
-
-
-
ACT0
ACT1
ACT2
BUS
BUS
BUS
RW
RW
RW
10
10
10
Normal Demultiplexed
Read/Write
Delay
Bus Cycle
CTL0
CTL1
CTL2
ALE
ALE
ALE
RW
RW
RW
9
9
9
8
8
8
-
-
-
Data
SFR
SFR
SFR
Data
7
7
7
BTYP
BTYP
BTYP
RW
RW
RW
ALE Lengthen Demultiplexed
6
6
6
MTT
MTT
MTT
RW
RW
RW
C0
C1
C2
5
5
5
Bus Cycle
Read/Write
RWD
RWD
RWD
Delay
RW
RW
RW
C0
C1
C2
4
4
4
3
3
3
Reset Value: 0000h
Reset Value: 0000h
Reset Value: 0xx0h
Data
2
2
2
Data
MCTC
MCTC
MCTC
RW
RW
RW
ST10F280
1
1
1
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0
0
0