ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 177

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ST10F280

Manufacturer Part Number
ST10F280
Description
MCU 16BIT 512K FLASH MAC 208-PBG
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F280

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, SSC
Peripherals
POR, PWM, WDT
Number Of I /o
143
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
18K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 32x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
208-PBGA
Processor Series
ST10F28x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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20.4.12 - CLKOUT and READY
V
Table 43 : CLKOUT and READY Characteristics
Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
t
t
t
t
t
t
t
t
t
t
t
t
29
30
31
32
33
34
35
36
37
58
59
60
DD
Symbol
= 5V
2. Demultiplexed bus is the worst case. For multiplexed bus 2 TCL are to be added to the maximum values. This adds even more
time for deactivating READY.
The 2t
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
A
and t
10%, V
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
Synchronous READY
setup time to CLKOUT
Synchronous READY
hold time after CLKOUT
Asynchronous READY
low time
Asynchronous READY
setup time
Asynchronous READY
hold time
Async. READY hold time after
RD, WR high (Demultiplexed
Bus)
C
refer to the next following bus cycle, t
SS
Parameter
= 0V, T
A
= -40 to +125°C, C
1)
1)
2)
Minimum
-2 + t
Maximum CPU Clock
12.5
12.5
F
25
35
refers to the current bus cycle.
4
3
2
2
0
A
L
= 40MHz
= 50pF
0 + 2t
Maximum
8 + t
A
25
2)
4
4
+ t C + t
A
F
2 TCL + 10
Minimum
TCL – 8.5
TCL – 9.5
-2 + t
2 TCL
1/2 TCL = 1 to 40MHz
12.5
12.5
Variable CPU Clock
2
2
0
A
+ 2t
TCL - 12.5
Maximum
A
8 + t
2TCL
+ t C + t
4
4
A
ST10F280
F
2)
177/186
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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