ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 179
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ST10F280
Manufacturer Part Number
ST10F280
Description
MCU 16BIT 512K FLASH MAC 208-PBG
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F280.pdf
(186 pages)
Specifications of ST10F280
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, SSC
Peripherals
POR, PWM, WDT
Number Of I /o
143
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
18K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 32x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
208-PBGA
Processor Series
ST10F28x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F280-B3
Manufacturer:
ST
Quantity:
6 221
Part Number:
ST10F280-B3
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
ST10F280-Q3TR
Manufacturer:
SONY
Quantity:
26
Part Number:
ST10F280-Q3TR
Manufacturer:
ST
Quantity:
20 000
20.4.13 - External Bus Arbitration
V
Note: 1. Partially tested, guaranteed by design characterization.
Figure 89 : External Bus Arbitration, Releasing the Bus
Notes: 1. The ST10F280 will complete the currently running bus cycle before granting bus access.
t
t
t
t
t
t
t
61
62
63
64
65
66
67
DD
Symbol
= 5V
CLKOUT
HOLD
HLDA
BREQ
CSx
(P6.x)
Others
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t
SR
CC
CC
CC
CC
CC
CC
10%, V
HOLD input setup time
to CLKOUT
CLKOUT to HLDA high
or BREQ low delay
CLKOUT to HLDA low
or BREQ high delay
CSx release
CSx drive
Other signals release
Other signals drive
SS
= 0V, T
Parameter
t
61
A
= -40 to +125°C, C
1)
1)
1
1
Minimum
Maximum CPU Clock
64
.
15
-4
-4
–
–
–
–
L
= 50pF
= 40MHz
t
66
t
63
Maximum
12.5
12.5
15
15
15
15
–
t
t
62
64
3)
2)
Minimum
1/2 TCL = 1 to 40MHz
Variable CPU Clock
15
-4
-4
–
–
–
–
Maximum
12.5
12.5
15
15
15
15
–
ST10F280
179/186
ns
ns
ns
ns
ns
ns
ns