ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 14

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
Table 1 : Ball Description (continued)
14/186
PORT1:
P1L.0 - P1L.7,
P1H.0 - P1H.7
XTAL1
XTAL2
RSTIN
RSTOUT
NMI
Symbol
Number
Ball
C11
B11
D10
C10
B10
A10
D9
C9
C8
D8
C7
D7
C5
C6
C4
A7
B7
A5
A6
A3
B4
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
I
I
I
PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise
programmable for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after switching from a
demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins
also serve for alternate functions:
P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7
P1H.0
P1H.1
P1H.2
P1H.3
P1H.4
P1H.5
P1H.6
P1H.7
XTAL1: Input to the oscillator amplifier and input to the internal clock generator
XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1, while leaving XTAL2
unconnected. Minimum and maximum high/low and rise/fall times specified in
the AC Characteristics must be observed.
Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a spec-
ified duration while the oscillator is running resets the ST10F280. An internal pul-
lup resistor permits power-on reset using only a capacitor connected to V
In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON regis-
ter), the RSTIN line is pulled low for the duration of the internal reset sequence.
Internal Reset Indication Output. This pin is set to a low level when the part is
executing either a hardware, a software or a watchdog timer reset. RSTOUT
remains low until the EINIT (end of initialization) instruction is executed.
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (power down) instruction is executed, the NMI pin must be low in
order to force the ST10F280 to go into power down mode. If NMI is high and
PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal
mode.
If not used, pin NMI should be pulled high externally.
CC24IO
CC25IO
CC26IO
CC27IO
CAPCOM2: CC24 Capture Input
CAPCOM2: CC25 Capture Input
CAPCOM2: CC26 Capture Input
CAPCOM2: CC27 Capture Input
Function
SS
.