ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 28

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
Table 3 : Instructions
Notes 1. Address bit A14, A15 and above are don’t care for coded address inputs.
28/186
Read/Reset
Read/Reset
Program Word
Block Erase
Chip Erase
Erase Suspend
Erase Resume
Set Block/Code
Protection
Read
Protection
Status
Block
Temporary
Unprotection
Code
Temporary
Unprotection
Code
Temporary
Protection
Instruction
2. X = Don’t Care.
3. WA = Write Address: address of memory location to be programmed.
4. WD = Write Data: 16-bit data to be programmed
5. Optional, additional blocks addresses must be entered within a time-out delay (96 µs) after last write entry, timeout status can be
verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
6. Read Data Polling or Toggle bit until Erase completes.
7. WPR = Write protection register. To protect code, bit 15 of WPR must be ‘0’. To protect block N (N=0,1,...), bit N of WPR must be
‘0’. Bit that are already at ‘0’ in protection register must also be ‘0’ in WPR, else a writing error will occurs (it is not possible to write a
‘1’ in a bit already programmed at ‘0’).
8. MEM = any address inside the Flash memory space. Absolute addressing mode must be used (MOV MEM, Rn), and instruction
must be executed from Flash memory space.
9. Odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 0002h, 0006h...
Mne
BTU
CTU
CTP
PW
RD
RD
CE
ER
RP
BE
ES
SP
Cycle
1+
3+
4
6
6
1
1
4
4
4
1
1
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
1
1
1
1
1
1
1
1
1
1
1
1
x2A54h
x2A54h
x2A54h
x1554h
x1554h
x1554h
x1554h
MEM
FFFFh
MEM
FFFBh
xxA8h
xxA8h
xxA8h
xxA8h
xxB0h
xxA8h
xxA8h
xxA8h
Cycle
xxF0h
xx30h
X
1
X
X
st
2
2
2
8
8
Read Memory Array until a new write cycle is initiated
Read until Toggle stops, then read or program all data needed
from block(s) not being erased then Resume Erase.
Read Data Polling or Toggle bit until Erase completes or Erase
is supended another time.
Write cycles must be executed from Flash.
Write cycles must be executed from Flash.
x2AA8h
x2AA8h
x2AA8h
x2AA8h
x15A8h
x15A8h
x15A8h
Cycle
xx54h
xx54h
xx54h
xx54h
xx54h
xx54h
xx54h
2
nd
x2A54h
x2A54h
x2A54h
x1554h
x1554h
x1554h
xxxxxh
xxA0h
xxC0h
xxC1h
xxF0h
Cycle
xx80h
xx80h
xx90h
3
rd
Read Memory Array until a new write
cycle is initiated
4
address
address
Any odd
Any odd
x1554h
x1554h
th
WPR
xxA8h
xxA8h
xxF0h
WD
Read
WA
word
word
PR
Cycle
X
2
3
4
7
9
9
Read Data Polling or
Toggle Bit until Program
completes.
Read Protection Register
until a new write cycle is
initiated.
x2AA8h
x2AA8h
Cycle
xx54h
xx54h
5
th
x1554h
Cycle
xx30h
xx10h
6
BA
th
Note
Cycle
xx30h
BA’
7
th
5
6