R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 153

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
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11.1.3
11.1.4
11.1.3.1
11.1.3.2
11.1.3.3
11.1.3.4
11.1.3.5
11.1.3.6
Special interrupts are non-maskable.
A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 14. Watchdog Timer.
An oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the
oscillation stop detection function, refer to 9. Clock Generation Circuit.
A voltage monitor 1/comparator A1 interrupt is generated by the voltage detection circuit or the comparator A.
A non-maskable or maskable interrupt can be selected by IRQ1SEL bit in the CMPA register. For details of the
voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 28.
Comparator A.
A voltage monitor 2/comparator A2 interrupt is generated by the voltage detection circuit or the comparator A.
A non-maskable or maskable interrupt can be selected by IRQ2SEL bit in the CMPA register. For details of the
voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 28.
Comparator A.
Do not use these interrupts. They are provided exclusively for use by development tools.
An address match interrupt is generated immediately before executing an instruction that is stored at an address
indicated by registers RMAD0 to RMAD1 if the AIER00 bit in the AIER0 register or the AIER10 bit in the
AIER1 register is set to 1 (address match interrupt enabled).
For details of the address match interrupt, refer to 11.6 Address Match Interrupt.
A peripheral function interrupt is generated by a peripheral function in the MCU. Peripheral function interrupts
are maskable. Refer to Table 11.2 Relocatable Vector Tables for sources of the corresponding peripheral
function interrupt. For details of peripheral functions, refer to the descriptions of individual peripheral
functions.
Special Interrupts
Peripheral Function Interrupts
Watchdog Timer Interrupt
Oscillation Stop Detection Interrupt
Voltage Monitor 1/Comparator A1 Interrupt
Voltage Monitor 2/Comparator A2 Interrupt
Single-Step Interrupt, and Address Break Interrupt
Address Match Interrupt
Preliminary specification
Specifications in this manual are tentative and subject to change.
Nov 05, 2008
11. Interrupts