R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 626

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

RENESAS TECHNICAL UPDATE
Figure 2.4 Timer RD Control Register 0, 1 (TRDCR0, TRDCR1) Setting
Notes:
Timer RD Control Register i (TRDCRi) (i = 0 or 1)
Address
Bit
Symbol
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR
2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2) in timer mode.
3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0
4. This setting is enabled when the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate
5. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
register is 1 (external clock input enabled).
(TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
synchronously).
Symbol Bit Name
CKEG0 External clock edge select bit
CKEG1
CCLR0 TRDi counter clear select bit
CCLR1
CCLR2
TCK0
TCK1
TCK2
0140h (TRDCR0), 0150h (TRDCR1)
b7
CCLR2
0
Count source select bit
b6
CCLR1
0
b5
CCLR0
0
TN-R8C-A001B/E
b4
CKEG1
0
(3)
Function
b2 b1 b0
b4 b3
b7 b6 b5
other timer RDi counter)
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRDCLK input
1 1 0: fOCO40M
1 1 1: fOCO-F
0 0: Count at the rising edge
0 1: Count at the falling edge
1 0: Count at both edges
1 1: Do not set.
0 0 0: Disable clear (free-running operation)
0 0 1: Clear by input capture in the TRDGRAi register
0 1 0: Clear by input capture in the TRDGRBi register
0 1 1: Synchronous clear (clear simultaneously with
1 0 0: Do not set.
1 0 1: Clear by input capture in the TRDGRCi register
1 1 0: Clear by input capture in the TRDGRDi register
1 1 1: Do not set.
b3
CKEG0
0
b2
TCK2
0
(5)
Do not set
(1)
b1
TCK1
0
(4)
or fC2
(2)
b0
TCK0
0
Date: Sep.24.2009
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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