R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 212

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 182 of 583
15.3.9
Table 15.9
Note:
Table 15.10
Data write
Operation
Data read
1. For the number of clock cycles required for data read/write, see Table 15.10 Number of Clock
Vector Read
Table 15.9 shows the Operations Following DTC Activation and Required Number of Cycles for each
operation.
Table 15.10 shows the Number of Clock Cycles Required for Data Transfers.
Data is transferred as described below, when the DTBLSj (j = 0 to 23) register = N,
(1) When N = 2n (even), two-byte transfers are performed n times.
(2) When N = 2n + 1 (odd), two-byte transfers are performed n times followed by one time of one-byte
From Tables 15.9 and 15.10, the total number of required execution cycles can be obtained by the following
formula:
Number of required execution cycles = 1 + Σ[formula A] + 2
Σ: Sum of the cycles for the number of transfer times performed by one activation source ([the number of
transfer times for which CHNE is set to 1] + 1)
(1) For N = 2n (even)
(2) For N = 2n+1 (odd)
J: Number of cycles required to read or write back control data
To read data from or write data to the register that to be accessed in 16-bit units, set an even value of 2 or greater
to the DTBLSj (j = 0 to 23) register.
The DTC performs accesses in 16-bit units.
Cycles Required for Data Transfers.
transfer.
Formula A = J + n • SK2 + n • SL2
Formula A = J + n • SK2 + 1 • SK1 + n • SL2 + 1 • SL1
1
1
1-byte SK1
2-byte SK2
1-byte SL1
2-byte SL2
Number of DTC Execution Cycles
Transfers
Unit of
Preliminary specification
Specifications in this manual are tentative and subject to change.
Operations Following DTC Activation and Required Number of Cycles
Number of Clock Cycles Required for Data Transfers
(During DTC Transfers) Internal ROM
Address
Even
Control Data Read
Internal RAM
1
1
Write (J)
1
1
Nov 05, 2008
5 to 7
5 to 7
Address
Odd
2
2
(Program ROM)
—
—
1
2
Data Read
(Note 1)
(Note 1)
(Data flash)
Internal
ROM
—
—
2
4
Address
Even
(Word Access)
2
2
SFR
Data Write
2
2
(Note 1)
(Note 1)
Address
Odd
4
4
Access)
(Byte
SFR
2
4
2
4
Internal Operation
(DTC control data area)
Address
Even
1
1
2
2
SFR
1
1
Address
Odd
15. DTC
2
2