R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 264
R5F21324ANSP#U1
Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet
1.R5F21322ANSPU1.pdf
(629 pages)
Specifications of R5F21324ANSP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 234 of 583
19.2.12 Timer RC Output Master Enable Register (TRCOER)
Note:
19.2.13 Timer RC Trigger Control Register (TRCADCR)
1. These bits are disabled for input pins set to the input capture function.
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0132h
Address 0133h
Symbol
Symbol
ADTRGAE A/D trigger A enable bit
ADTRGBE A/D trigger B enable bit
ADTRGCE A/D trigger C enable bit
ADTRGDE A/D trigger D enable bit
Symbol
Bit
Bit
Symbol
PTO
EC
ED
EA
EB
—
—
—
—
—
—
—
Preliminary specification
Specifications in this manual are tentative and subject to change.
PTO
b7
b7
—
0
0
TRCIOA output disable bit
TRCIOB output disable bit
TRCIOC output disable bit
TRCIOD output disable bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
INT0 of pulse output forced cutoff
signal input enabled bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b6
b6
—
—
1
0
Nov 05, 2008
Bit Name
Bit Name
b5
—
b5
—
1
0
(1)
(1)
(1)
(1)
b4
b4
—
—
1
0
ADTRGDE ADTRGCE ADTRGBE ADTRGAE
0: Enable output
1: Disable output (The TRCIOA pin is used as a
0: Enable output
1: Disable output (The TRCIOB pin is used as a
0: Enable output
1: Disable output (The TRCIOC pin is used as a
0: Enable output
1: Disable output (The TRCIOD pin is used as a
0: Pulse output forced cutoff input disabled
1: Pulse output forced cutoff input enabled
0: A/D trigger disabled
1: A/D trigger generated at compare match with
0: A/D trigger disabled
1: A/D trigger generated at compare match with
0: A/D trigger disabled
1: A/D trigger generated at compare match with
0: A/D trigger disabled
1: A/D trigger generated at compare match with
ED
b3
registers TRC and TRCGRA
registers TRC and TRCGRB
registers TRC and TRCGRC
registers TRC and TRCGRD
1
programmable I/O port.)
programmable I/O port.)
programmable I/O port.)
programmable I/O port.)
(Bits EA, EB, EC, and ED are set to 1 (disable
output) when “L” is applied to the INT0 pin)
b3
0
EC
b2
1
b2
0
Function
Function
EB
b1
1
b1
0
EA
b0
1
b0
0
19. Timer RC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
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