R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 586

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324ANSP#U1

Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet

Specifications of R5F21324ANSP#U1

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21324ANSP#U1
Manufacturer:
Renesas Electronics America
Quantity:
135
Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 556 of 583
33.2
33.2.1
33.2.2
33.2.3
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the IR bit for the acknowledged interrupt is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
Set a value in the SP before an interrupt is acknowledged. The SP is set to 0000h after a reset. If an interrupt is
acknowledged before setting a value in the SP, the program may run out of control.
Either the “L” level width or “H” level width shown in the Electrical Characteristics is required for the signal
input to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 32.22 (VCC = 5V), Table 32.28 (VCC = 3V), Table 32.34 (VCC = 2.2V) External
Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3).
Notes on Interrupts
Reading Address 00000h
SP Setting
External Interrupt and Key Input Interrupt
Preliminary specification
Specifications in this manual are tentative and subject to change.
Nov 05, 2008
33. Usage Notes

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