R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 57

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 27 of 583
Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after
Reset, Figure 5.3 shows the Reset Sequence.
Figure 5.2
Figure 5.3
Table 5.2
Internal reset
signal
P1, P3_3 to P3_5, P3_7
P4_2, P4_5 to P4_7
CPU clock
Address
(internal address
signal)
RESET pin
fOCO-S
Notes:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same time.
Pin Name
CPU Register Status after Reset
Reset Sequence
Preliminary specification
Specifications in this manual are tentative and subject to change.
Pin Functions while RESET Pin Level is “L”
10 cycles or more are needed
b15
fOCO-S clock × 32 cycles
IPL
b19
Content of addresses 0FFFEh to 0FFFCh
Start time of flash memory
(CPU clock × 148 cycles)
Nov 05, 2008
b15
b15
b15
Input port
Input port
(1)
b8
(2)
00000h
U
b7
I
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
O
Pin Function
CPU clock × 28 cycles
B
S
Z
D
C
b0
b0
b0
b0
b0
0FFFCh
Interrupt table register (INTB)
Program counter (PC)
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
Flag register (FLG)
Data register (R0)
Data register (R1)
Data register (R2)
Data register (R3)
Address register (A0)
Address register (A1)
Frame base register (FB)
0FFFDh
0FFFEh
Content of reset vector
5. Resets