R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 115

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 12.7
Table 12.5
Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 2, Address Break
Software, Address Match, Single-Step
12.1.6.5
12.1.6.6
Figure 12.7 shows an Interrupt Response Time. The interrupt response time is the period between an interrupt
request generation and the execution of the first instruction in an interrupt routine. An interrupt response time
includes the period between an interrupt request generation and the completed execution of an instruction
(refer to (a) in Figure 12.7) and the period required to perform an interrupt sequence (20 cycles, refer to (b) in
Figure 12.7).
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt and special interrupt request are acknowledged, the level listed in Table 12.5 is set to
the IPL.
Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
Interrupt request is generated Interrupt request is acknowledged
Interrupt Response Time
IPL Change when Interrupt Request is Acknowledged
IPL Value When Software or Special Interrupt Is Acknowledged
Interrupt Response Time
(a) Period between an interrupt request generation and the completed execution of an
(b) 21 cycles for address match and single-step interrupts.
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instruction. The length of this time varies depending on the instruction being executed.
The DIVX instruction requires the longest time; 30 cycles (no wait and when the register
is set as the divisor)
Instruction
(a)
Interrupt Sources
Interrupt response time
Interrupt sequence
20 Cycles (b)
interrupt routine
Instruction in
Value Set to IPL
Time
Not changed
7
12. Interrupts