R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 378

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
18. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares the pins with P0_0 to P0_7, P1_0 to P1_3. Therefore, when using these pins, ensure
the corresponding port direction bits are set to 0 (input mode).
When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (Vref unconnected), so that no
current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The result of A/D conversion is stored in the AD register.
Table 18.1 lists the Performance of A/D Converter. Figure 18.1 shows the Block Diagram of A/D Converter. Figure
18.2 and Figure 18.3 show the A/D converter-related registers.
Table 18.1
NOTES:
A/D Conversion Method
Analog Input Voltage
Operating Clock φAD
Resolution
Absolute Accuracy
Operating Mode
Analog Input Pin
A/D Conversion Start Condition • Software trigger
Conversion Rate Per Pin
1. Analog input voltage does not depend on use of sample and hold function.
2. The frequency of φAD must be 10 MHz or below.
3. In repeat mode, only 8-bit mode can be used.
When analog input voltage exceeds reference voltage, A/D conversion result is 3FFh in 10-bit
mode, FFh in 8-bit mode.
Without sample and hold function, the φAD frequency should be 250 kHz or above.
With the sample and hold function, the φAD frequency should be 1 MHz or above.
Item
Performance of A/D Converter
(1)
(2)
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Successive approximation (with capacitive coupling amplifier)
0 V to AVCC
4.2 V ≤ AVCC ≤ 5.5 V f1, f2, f4, fOCO-F
2.7 V ≤ AVCC < 4.2 V f2, f4, fOCO-F
8 bit or 10 bit is selectable
AVCC = Vref = 5 V, φAD = 10MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB
AVCC = Vref = 3.3 V, φAD = 10MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
One-shot and repeat modes
12 pins (AN0 to AN11)
• Capture
• Without sample and hold function
• With sample and hold function
Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)
Timer RD interrupt request is generated while the ADST bit is set to 1
8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles
8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles
(3)
Performance
18. A/D Converter