R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 371

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 17.8
Timer RA Set to pulse width measurement mode
Timer RA Set the pulse width measurement level low
Timer RA Set the INT1/TRAIO pin to P1_5
Timer RA Set the count source (f1, f2, f8, fOCO)
Timer RA Set the Synch Break width
Hardware LIN Set the LIN operation to stop
Hardware LIN Set to slave mode
Hardware LIN Set the LIN operation to start
Hardware LIN Set the RXD0 input unmasking timing
Hardware LIN Set the register to enable interrupts
Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
TEDGSEL bit in the TRAIOC register ← 0
TIOSEL bit in the TRAIOC register ← 1
TCK0 to 2 bits in the TRAMR register
TRAPRE register
TRA register
Example of Header Field Reception Flowchart (1)
LINE bit in the LINCR register ← 0
MST bit in the LINCR register ← 0
LINE bit in the LINCR register ← 1
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
Page 353 of 458
A
Set the count source and the TRA
and TRAPRE registers as suitable
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal too is
input to UART0.
17. Hardware LIN