R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 359

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 16.47
NOTES:
1. Do not generate the interrupt during the process of step (1) to (3).
2. When receiving 1 byte, skip step (2) to (6) after (1) and jump to process of step (7).
Process of step (8) is dummy-read in the ICDRR register.
ICSR register
ICCR1 register
ICSR register
ICIER register
ICIER register
ICCR1 register
ICSR register
ICCR2 register
ICCR1 register
ICCR1 register
Example of Register Setting in Master Receive Mode (I
Read RDRF bit in ICSR register
Read RDRF bit in ICSR register
Read STOP bit in ICSR register
Dummy-read in ICDRR register
No
No
No
Read ICDRR register
Read ICDRR register
Read ICDRR register
Master receive mode
RDRF = 1 ?
Yes
RDRF = 1 ?
Yes
Yes
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Last receive
STOP = 1 ?
ACKBT bit ← 0
ACKBT bit ← 1
TEND bit ← 0
TDRE bit ← 0
- 1 ?
RCVD bit ← 1
STOP bit ← 0
End
RCVD bit ← 0
TRS bit ← 0
BBSY bit ← 0
SCP bit ← 0
MST bit ← 0
No
Yes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(1) Set the TEND bit to 0 and set to master receive mode.
(2) Set the ACKBT bit to the transmit device
(3) Dummy-read to the ICDRR register
(4) Wait for 1 byte to be received
(5) Judge (last receive - 1)
(6) Read the receive data
(7) Set the ACKBT bit of the last byte and set to disable the
(8) Read the receive data of (last byte - 1)
(9) Wait the last byte is received
(10) Set the STOP bit to 0
(11) Generate the stop condition
(12) Wait the stop condition is generated
(13) Read the receive data of the last byte
(14) Set the RCVD bit to 0
(15) Set to slave receive mode
continuous receive (RCVD = 1)
Set the TDRE bit to 0
16. Clock Synchronous Serial Interface
(1,2)
2
C Bus Interface Mode)
(2)
(1)
(1)