R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 197

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.41
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4
NOTES:
1.
2.
3.
4. Edge selected by bits IOk1 to IOk0 (k = C or D) in the TRDIORCi register.
Nothing is assigned to the b5 in the TRDSR0 register. When w riting to the b5, w rite 0. When reading, its content is 1.
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and w riting 0 to the same bit.
• This bit remains unchanged even if the read result is 0 and w riting 0 to the same bit. (This bit remains 1 even if this
• This bit remains unchanged w hen w riting 1.
Edge selected by bits IOj1 to IOj0 (j = A or B) in the TRDIORAi register.
Including w hen the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as the buffer register).
bit is set to 1 from 0 after reading, and w riting 0.)
b3 b2
b1 b0
Registers TRDSR0 to TRDSR1 in Input Capture Function
Bit Symbol
(b7 - b6)
TRDSR0
TRDSR1
Symbol
IMFA
IMFB
IMFC
IMFD
OVF
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UDF
—
Input capture/compare match flag
A
Input capture/compare match flag
B
Input capture/compare match flag
C
Input capture/compare match flag
D
Overflow flag
Underflow flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Address
Bit Name
0143h
0153h
(1)
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
TRDSR0 register:
fOCO128 signal edge w hen the IOA3 bit in the
TRDIORA0 register is set to 0 (fOCO128
signal) TRDIOA0 pin input edge w hen the
IOA3 bit in the TRDIORA0 register is set to 1
(TRDIOA0 input)
TRDSR1 register:
Input edge of TRDIOA1 pin.
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
Input edge of TRDIOBi pin.
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
Input edge of TRDIOCi pin.
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
Input edge of TRDIODi pin.
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
When the TRDi register overflow s
This bit is disabled in the input capture
function.
(3)
After Reset
11100000b
11000000b
(2)
(2)
(2)
(2)
(2)
Function
(3)
(4)
(4)
(3)
14. Timers
RW
RW
RW
RW
RW
RW
RW
—