R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 494

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
1.00
REVISION HISTORY
Nov 15, 2006
Date
Page
221
222
232
235
236
239
249
265
266
279
283
311
338
347
Table 14.31 Complementary PWM Mode Specifications, on the 3rd line from the
bottom;
Figure 14.85 TRDSTR Register in Complementary PWM Mode → Figure 14.85
TRDSTR Register in Complementary PWM Mode replaced.
corrected.
Figure 14.98 Operating Example of Complementary PWM Mode → Figure 14.95
Operating Example of Complementary PWM Mode replaced.
Table 14.33 PWM3 Mode Specifications, on the bottom line;
Figure 14.100 TRDSTR Register in PWM3 Mode → Figure 14.97 TRDSTR
Register in PWM3 Mode replaced.
corrected.
Figure 14.103 TRDOCR Register in PWM3 Mode → Figure 14.100 TRDOCR
Register in PWM3 Mode replaced.
NOTE2 added.
14.3.12.4 Count Source Switch;
14.3.12.7 Complementary PWM Mode, on the bottom line;
Figure 15.4 UiMR Register (i = 0 or 1);
corrected.
Figure 15.5 Registers UiC0 and UiC1 (i = 0 or 1);
Table 16.1 Mode Selections revised.
Figure 16.3 SSCRL Register; NOTE2 revised
Figure 16.23 External Circuit Connection Example of Pins SCL and SDA
revised.
Figure 16.47 Example of Register Setting in Master Receive Mode (I
Interface Mode);
corrected.
Figure 17.5 Example of Header Field Transmission Flowchart (1);
Hard ware LIN Clear the status flags; “~ in LINST register” → “~ in LINST
register: 0” corrected.
Timer RD Start Register
“i = 0 to 2, j = either A, B, C or D” → “i = 0 or 1, j = either A, B, C or D” corrected.
Timer RD Start Register
“TRD1 count start bit
“j = either A, B, C or D” → “i = 0 or 1, j = either A, B, C or D” corrected.
“TRD1 count start bit
“count clock source” → “count source” corrected.
“Do not use the TRDGRC0 register in complementary PWM mode.” deleted.
“Serial Interface mode select bit
UARTi Transmit/Receive Control Register 1 (i = 0 or 1) revised.
NOTE2 added.
(1) “Set the ~ master receive mode ~” → “Set the ~ master transmit mode ~”
R8C/20 Group, R8C/21 Group Hardware Manual
C - 18
(5)
(5)
” → “TRD1 count start flag
” → “TRD1 count start flag
(1)
(1)
; “TRD0 count start bit
; TRD0 count start bit
Description
(2,4)
Summary
” → “Serial I/O mode select bit
(4)
(4)
(5)
(5)
” → “TRD0 count start flag
→ “TRD0 count start flag
” corrected.
” corrected.
(2,4)
2
C Bus
”
(4)
(4)
”
”