R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 224

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.68
Timer RD Output Control Register
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4
NOTES:
b7 b6 b5 b4
NOTES:
0 0 1
1.
2.
1.
2. This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR
Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
stops).
When the pin functions are w aveform output (refer to Table 14.13 to 14.15 ; Table 14.17 to 14.19 ) and the TRDOCR
register is set, the initial output level is output.
This bit is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
register is set to 1 (external clock input enabled).
0
b3 b2
b3 b2
b1 b0
b1 b0
Registers TRDOCR and TRDCR0 to TRDCR1 in PWM Mode
0
Bit Symbol
Bit Symbol
TRDOCR
TRDCR0
TRDCR1
Symbol
Symbol
CKEG0
CKEG1
CCLR0
CCLR1
CCLR2
TOA0
TOB0
TOC0
TOD0
TOA1
TOB1
TOC1
TOD1
TCK0
TCK1
TCK2
Page 206 of 458
TRDIOA0 output level selection bit
TRDIOB0 output level selection bit
TRDIOC0 initial output level selection bit
TRDIOD0 initial output level selection bit
TRDIOA1 initial output level selection bit
TRDIOB1 initial output level selection bit
TRDIOC1 initial output level selection bit
TRDIOD1 initial output level selection bit
Count source selection bit
External clock edge selection
bit
TRDi counter clear selection bit
(2)
(1)
Address
Bit Name
0140h
0150h
Address
Bit Name
013Dh
(2)
b2 b1 b0
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRDCLK input
1 1 0 : fOCO40M
1 1 1 : Do not set
b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set
Set to 001b (the TRDi register clear at the
compare match w ith TRDGRAi register) in PWM
mode.
(2)
(2)
(2)
(2)
(2)
Set this bit to 0 (enable
output) in PWM mode
0 : Initial output is inactive
1 : Initial output is active level
Set this bit to 0 (enable
output) in PWM mode
0 : Inactive level
1 : Active level
After Reset
Function
level
(1)
00h
00h
After Reset
Function
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW