R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 258

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.100 Registers TRDMR and TRDFCR in PWM3 Mode
Timer RD Function Control Register
Timer RD Mode Register
b7 b6 b5 b4
b7 b6 b5 b4
NOTES:
0 0
1.
2.
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops).
When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
b3 b2
b3 b2
b1 b0
b1 b0
0 0
Bit Symbol
Bit Symbol
(b3 - b1)
TRDFCR
ADTRG
Symbol
TRDMR
Symbol
STCLK
ADEG
PWM3
SYNC
CMD0
CMD1
OLS0
OLS1
BFC0
BFD0
BFC1
BFD1
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Combination mode selection bit
Normal-phase output level selection bit
(enabled in reset synchronous PWM
mode or complementary PWM mode)
Counter-phase output level selection bit
(enabled in reset synchronous PWM
mode or complementary PWM mode)
A/D trigger enable bit
(enabled in complementary PWM mode)
A/D trigger edge selection bit
(enabled in complementary PWM mode)
External clock input selection bit
PWM3 mode selection bit
Timer RD synchronous bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRDGRC0 register function
selection bit
TRDGRD0 register function
selection bit
TRDGRC1 register function
selection bit
TRDGRD1 register function
selection bit
Address
Bit Name
0138h
Address
Bit Name
013Ah
(2)
(1)
This bit is disabled in PWM3 mode.
0 : General register
1 : Buffer register of TRDGRA0 register
0 : General register
1 : Buffer register of TRDGRB0 register
0 : General register
1 : Buffer register of TRDGRA1 register
0 : General register
1 : Buffer register of TRDGRB1 register
Set to 00b (timer mode, PWM mode, or
PWM3 mode) in PWM3 mode.
This bit is disabled in PWM3 mode.
This bit is disabled in PWM3 mode.
This bit is disabled in PWM3 mode.
This bit is disabled in PWM3 mode.
Set this bit to 0 (external clock input
disabled) in PWM3 mode.
Set this bit to 0 (PWM3 mode) in PWM3
mode.
After Reset
00001110b
Function
After Reset
10000000b
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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