R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 358

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 16.46
16.3.7
Figure 16.46 to Figure 16.49 show the Examples of Register Setting When Using I
Examples of Register Setting
Example of Register Setting in Master Transmit Mode (I
ICCR1 register
ICCR2 register
ICSR register
ICSR register
ICCR2 register
ICCR1 register
ICSR register
Read STOP bit in ICSR register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Read ACKBR bit in ICIER register
Read BBSY bit in ICCR2 register
Read TEND bit in ICSR register
Read TDRE bit in ICSR register
Read TEND bit in ICSR register
Page 340 of 458
No
No
No
No
No
No
ACKBR = 0 ?
Initial setting
BBSY = 0 ?
Yes
TEND = 1 ?
TDRE = 1 ?
TEND = 1 ?
Last byte ?
STOP = 1 ?
TDRE bit ← 0
BBSY bit ← 1
Transmit
BBSY bit ← 0
MST bit ← 1
mode ?
TRS bit ← 1
SCP bit ← 0
TEND bit ← 0
STOP bit ← 0
SCP bit ← 0
TRS bit ← 0
MST bit ← 0
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Master receive
mode
- Set the STOP bit in the ICSR register to 0.
- Set the IICSEL bit in the PMR register to 1.
(1) Judge the state of the SCL and SDA lines
(2) Set to master transmit mode
(3) Generate the start condition
(4) Set the transmit data of the 1st byte
(5) Wait for 1 byte to be transmitted
(6) Judge the ACKBR bit from the specified slave device
(7) Set the transmit data after 2nd byte (except the last byte)
(8) Wait the ICDRT register is empty
(9) Set the transmit data of the last byte
(10) Wait for the transmit end of the last byte
(11) Set the TEND bit to 0
(12) Set the STOP bit to 0
(13) Generate the stop condition
(14) Wait the stop condition is generated
(15) Set to slave receive mode
(slave address + R/W)
Set the TDRE bit to 0
16. Clock Synchronous Serial Interface
2
C Bus Interface Mode)
2
C Bus Interface.