R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 368

MCU FLASH 96K 5K CMOS 48-LQFP

R5F2121AJFP#U0

Manufacturer Part Number
R5F2121AJFP#U0
Description
MCU FLASH 96K 5K CMOS 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/21r
Datasheet

Specifications of R5F2121AJFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Manufacturer
Quantity
Price
Company:
Part Number:
R5F2121AJFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R5F2121AJFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 17.5
Timer RA Set to timer mode
Timer RA Set the pulse output level from low to start
Timer RA Set the INT1/TRAIO pin to P1_5
Timer RA Set the count source (f1, f2, f8, fOCO)
Timer RA Set the Synch Break width
UART0
UART0
UART0
Hardware LIN Set the LIN operation to stop
Hardware LIN Set to master mode
Hardware LIN Set the LIN operation to start
Hardware LIN Set the register to enable interrupts
Hardware LIN Clear the status flags
TMOD0 to 2 bits in TRAMR register ← 000b
TEDGSEL bit in TRAIOC register ← 1
TIOSEL bit in TRAIOC register ← 1
TCK0 to 2 bits in TRAMR register
TRAPRE register
TRA register
Set to transmit/receive mode
(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
UART0 Set the BRG count source (f1, f8, f32)
U0C0CLK0 to 1 bit
UART0 Set the bit rate
U0BRG register
Example of Header Field Transmission Flowchart (1)
LINE bit in LINCR register ← 0
MST bit in LINCR register ← 1
LINE bit in LINCR register ← 1
(Bus collision detection, Synch Break detection,
Synch Field measurement)
BCIE, SBIE, SFIE bits in LINCR register
(Bus collision detection, Synch Break detection,
Synch Field measurement)
B2CLR, B1CLR, B0CLR bits in LINST register ← 1
Page 350 of 458
A
Set the TIOSEL bit in the
TRAIOC register to 1 in the
hardware LIN function.
Set the count source and the
TRA and TRAPRE registers
as suitable for the Synch
Break period.
Set the BRG count source
and U0BRG register as
appropriate for the bit rate.
During master mode, the
Synch Field measurement-
completed interrupt cannot be
used.
17. Hardware LIN

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