MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 556

• Manufacturer Part Number: MC9S12DT256MPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DT256MPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 5 V to 2.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 12KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.1.3
Figure 14-1
REG consists of two parallel subblocks, REG1 and REG2, providing two independent output voltages.
556
V
V
V
DDR
DDA
SSA
Bus Clock
Block Diagram
shows the function principle of VREG_3V3 by means of a block diagram. The regulator core
V
REGEN
LVD
LVD: Low-Voltage Detect
LVR: Low-Voltage Reset
POR: Power-On Reset
Figure 14-1. VREG_3V3 Block Diagram
CTRL
MC9S12XDP512 Data Sheet, Rev. 2.21
API
Rate
Select
REG2
REG1
REG: Regulator Core
CTRL: Regulator Control
API: Auto. Periodical Interrupt
VBG
API
LVR
PIN
LVR
API
LVI
POR
Freescale Semiconductor
V
V
V
POR
V
DDPLL
SSPLL
DD
SS