MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 696

IC MCU 256K FLASH 25MHZ 112-LQFP

MC9S12DT256MPVE

Manufacturer Part Number
MC9S12DT256MPVE
Description
IC MCU 256K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12DT256MPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
PWM, WDT
Number Of I /o
91
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.25 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12D
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
91
Number Of Timers
1
Operating Supply Voltage
5 V to 2.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68KIT912DP256
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
12KB
Cpu Speed
25MHz
No. Of Timers
1
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.1
Read: Anytime
Write: Bits 7,1,0 anytime, Bit 6 can be written anytime but always reads back as 0.
698
Address
0x002A
0x002B
0x002C
0x002D
0x002E
0x0029
0x002F
0x0020
Reset
W
R
Bits 5:2 anytime DBG is not armed.
DBGXDHM
DBGXDLM
DBGXAM
DBGXDH
DBGXAH
DBGXDL
Register
DBGXAL
ARM
Name
Debug Control Register 1 (DBGC1)
0
7
When disarming the DBG by clearing ARM with software, the contents of
bits[5:2] are not affected by the write, since up until the write operation,
ARM=1 preventing these bits from being written. These bits must be cleared
using a second write if required.
W
W
W
W
W
W
W
R
R
R
R
R
R
R
TRIG
0
0
6
Bit 15
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Figure 19-2. DBG Register Summary (continued)
0
Figure 19-3. Debug Control Register (DBGC1)
XGSBPE
MC9S12XDP512 Data Sheet, Rev. 2.21
= Unimplemented or Reserved
Bit 22
0
5
14
14
14
6
6
6
6
BDM
21
13
13
13
NOTE
5
5
5
5
0
4
20
12
12
12
4
4
4
4
0
3
DBGBRK
19
11
11
11
3
3
3
3
0
2
18
10
10
10
2
2
2
2
Freescale Semiconductor
0
1
17
1
9
1
9
1
9
1
COMRV
Bit 16
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
0
0

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