MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 667
MC9S12DT256MPVE
Manufacturer Part Number
MC9S12DT256MPVE
Description
IC MCU 256K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S912XDG128F2MAL.pdf
(1348 pages)
Specifications of MC9S12DT256MPVE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
PWM, WDT
Number Of I /o
91
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.25 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12D
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
91
Number Of Timers
1
Operating Supply Voltage
5 V to 2.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68KIT912DP256
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
12KB
Cpu Speed
25MHz
No. Of Timers
1
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12DT256MPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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18.3.2.8
Read: Anytime
Write: Anytime
These eight index bits are used to page 16 KByte blocks into the Flash page window located in the local
(CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see
accessing up to 4 Mbytes of Flash (in the Global map) within the 64 KByte Local map. The PPAGE age
index register is effectively used to construct paged Flash addresses in the Local map format. The CPU has
special access to read and write this register directly during execution of CALL and RTC instructions. .
Freescale Semiconductor
Address: 0x0030
Reset
W
R
PIX7
Program Page Index Register (PPAGE)
1
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
1
Bit21
PIX6
1
6
Figure 18-15. Program Page Index Register (PPAGE)
PPAGE Register [7:0]
Figure 18-16. PPAGE Address Mapping
MC9S12XDP512 Data Sheet, Rev. 2.21
PIX5
1
5
Global Address [22:0]
CAUTION
Bit14
PIX4
NOTE
1
4
Bit13
PIX3
Address: CPU Local Address
1
3
Chapter 18 Memory Mapping Control (S12XMMCV3)
Address [13:0]
or BDM Local Address
PIX2
1
2
Figure
18-16). This supports
Bit0
PIX1
1
1
PIX0
0
0
667
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