MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 558

• Manufacturer Part Number: MC9S12DT256MPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DT256MPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 5 V to 2.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 12KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.2.4
Signals V
PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors
(220 nF, X7R ceramic).
In Shutdown Mode, an external supply driving V
14.2.5
This optional signal is used to shutdown VREG_3V3. In that case, V
provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high, the
VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode.
For the connectivity of VREGEN, see device specification.
14.3
This section provides a detailed description of all registers accessible in VREG_3V3.
If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within
it’s memory slice.
14.3.1
Table 14-2
558
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
DDPLL
Memory Map and Register Definition
Offset
provides an overview of all used registers.
VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins
V
Module Memory Map
REGEN —
is not supported while MCU is powered.
Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa
/V
SSPLL
are the secondary outputs of VREG_3V3 that provide the power supply for the
Autonomous Periodical Interrupt Trimming Register (VREGAPITR)
Optional Regulator Enable Pin
Autonomous Periodical Interrupt Control Register (VREGAPICL)
Autonomous Periodical Interrupt Period High (VREGAPIRH)
Autonomous Periodical Interrupt Period Low (VREGAPIRL)
MC9S12XDP512 Data Sheet, Rev. 2.21
HT Control Register (VREGHTCL)
Control Register (VREGCTRL)
Table 14-2. Memory Map
Reserved 06
Reserved 07
DDPLL
NOTE
Use
/V
SSPLL
can replace the voltage regulator.
DD
/V
SS
and V
DDPLL
Freescale Semiconductor
/V
Access
SSPLL
R/W
R/W
R/W
R/W
R/W
—
—
—
must be