M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 127

• Manufacturer Part Number: M30835FJGP#U3
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 10.7 Stack States
2
0
10.6.6 Saving a Register
10.6.7 Restoration from Interrupt Routine
1
9
C
3 .
B
In the interrupt sequence, the FLG register and PC are saved to the stack.
After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32
bits, are saved to the stack. Figure 10.7 shows the stack state before and after an interrupt request is
acknowledged.
Other important registers are saved by program at the beginning of an interrupt service routine. The
PUSHM instruction can save all registers except SP.
Refer to 10.4 High-Speed Interrupt for the high-speed interrupt.
When the REIT instruction is executed at the end of an interrupt service routine, the FLG register and PC,
which have been saved to the stack, are automatically restored. The program, executed before an interrupt
request has been acknowledged, starts running again. Refer to 10.4 High-Speed Interrupt for the high-
speed interrupt.
Restore registers saved by program in an interrupt service routine by the POPM instruction or others
before the REIT and FREIT instructions. Register bank is switched back to the bank used prior to the
interrupt sequence by the REIT or FREIT instruction.
8 /
Stack state before an interrupt request is acknowledged
0
1
3
0
Address
3
J
G
4
a
0 -
n
o r
m-6
m-5
m–4
m–3
m–2
m–1
m
m+1
3 .
1
u
, 1
3
p
1
MSB
2
(
M
0
0
3
6
Content of
previous stack
Content of
previous stack
2
C
The Stack
8 /
Page 102
, 3
M
3
2
C
f o
8 /
4
3
8
) T
8
LSB
[SP]
SP value before
interrupt is
generated
Stack state after an interrupt request is acknowledged
Address
m-6
m-5
m–4
m–3
m–2
m–1
m
m+1
MSB
Content of
previous stack
Content of
previous stack
The Stack
FLG
PC
PC
FLG
PC
00
M
16
L
H
L
H
LSB
[SP]
New SP value
10. Interrupts