M30835FJGP#U3 Renesas Electronics America, M30835FJGP#U3 Datasheet - Page 275

• Manufacturer Part Number: M30835FJGP#U3
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
2
0
Figure 21.2 Intelligent I/O Group 1 Block Diagram
1
9
C
3 .
B
(Note 2)
8 /
0
1
Waveform generation match signal from
the group 0 (For cascaded connection)
Time measurement trigger from
the group 0 (For cascaded connection)
3
0
3
J
G
4
a
0 -
n
o r
Two-phase pulse
signal is applied
f1
INPC1
ISCLK1
INPC1
ISRxD1
3 .
1
INPC1
INPC1
u
, 1
3
NOTES:
p
1
2
1
/
/
1. The G1TM0 register can be used in a 32-bit cascaded connection only.
2. These pins are not connected to external pins in the 100-pin package.
3. Each register is in a reset state after the G1BCR0 register supplies the
4. See Figure 10.14.
6
7
2
(
M
0
clock.
0
G1RI register
3
Digital
Digital
Digital
Digital
6
Receive
Receive
filter
filter
filter
filter
register
2
buffer
C
BCK1 to BCK0
11
10
Page 250
8 /
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
DF1 to DF0
DF1 to DF0
DF1 to DF0
DF1 to DF0
BT1S
BTS
1
1
1
1
, 3
BT1
BT1
BT1
BT1
External clock
External clock
1
M
00
00
00
00
RXSL
ch0
ch3
ch1
ch2
ch3
0
3
2
Request from the INT pin
selector
selector
Request from the group0
C
CTS1 to CTS0
CTS1 to CTS0
select
CTS1 to CTS0
select
CTS1 to CTS0
Clock
Clock
select
select
Edge
Edge
f o
Edge
Edge
8 /
Receive operation clock
DIV4 to DIV0
4
by 2(n+1)
Polarity
inverse
Divider
3
IPOL
8
operation clock
function
function
) T
Transmit
8
Gate
Gate
1
1
GT
GT
(Receive data register)
G1CMP3 register
0
0
(Transmit buffer register)
G1CMP3 register
G1DR register
G1CMP3 register
G1TB register
G1CMP3 register
register
register
Request by matching the base timer with the G1PO0 register
overflow of bit 15 in
the group0 base timer
buffer
Clock wait
Shift
Transmit
Transmit
register
control
circuit
buffer
Prescaler
Prescaler
function
function
f
BT1
1
1
PR
PR
0
0
DIV4 to DIV0, BCK1 to BCK0 : Bits in the G1BCR0 register
CAS, BTS : Bits in the G1BCR1 register
BT1S : Bit in the BTSR register
CTS1 and CTS0, DF1 and DF0, GT, PR : Bits in the G1TMCRj register (j = 0 to 7)
MOD2 to MOD0 : Bits in the G1POCRj register
TXSL, RXSL : Bits in the G1EMR register
generation circuit
generation circuit
generation circuit
G1RCRC
CAS
Bit insert circuit
register
Transmit latch
1
0
0
0
0
0
0
0
0
Bit insert
1
0
1
1
1
1
1
1
1
Start bit
Stop bit
Start bit
Stop bit
check
check
check
Group1 base timer reset
SOF
Comparator
Arbitration
Comparator
generation circuit
Comparator
G1TM0, G1PO0
register
G1TM1, G1PO1
register
G1TM2, G1PO2
register
G1TM3, G1PO3
register
G1TM4, G1PO4
register
G1TM5, G1PO5
register
G1TM6, G1PO6
register
Receive data
Comparator
selector
Base timer
Data
selector
generation circuit
Data
Transmit data
(Note 1)
G1TCRC
register
Transmission
Base timer interrupt request (BT1R)
Overflow of bit 15 in the base timer
Reception
G1TO register
interrupt
PWM
output
PWM
output
PWM
output
PWM
output
G1RB register
Special
TXSL
check
Transmit
Transmit
register
Receive
Receive
register
buffer
buffer
1
0
000 to 010
Polarity
inverse
OPOL
000 to 010
111
to MOD0
MOD2
Ch0 to ch7
interrupt request signal
OUTC1
OUTC1
OUTC1
OUTC1
OUTC1
Transmit interrupt request
(SIO1TR)
(SIO1RR)
(SRT1R)
(G1RIR)
MOD2 to MOD0
HDLC data transmit
interrupt request
Receive interrupt
request
Special communication
interrupt request
HDLC data receive
interrupt request
(G1TOR)
111
21. Intelligent I/O
3
4
5
6
7
(4)
(4)
(4)
OUTC1
BE1
OUTC1
OUTC1
(4)
(4)
(4)
OUT
(Note 2)
0
1
2
/ISTxD1/
/ISCLK1